F2_INT=F2_INT_0, ECC_INT=ECC_INT_0, DRDY=DRDY_0, SF_OR_INT=SF_OR_INT_0, DMA_TSF_DONE_FB2=DMA_TSF_DONE_FB2_0, SOF_INT=SOF_INT_0, COF_INT=COF_INT_0, RF_OR_INT=RF_OR_INT_0, F1_INT=F1_INT_0, EOF_INT=EOF_INT_0, RxFF_INT=RxFF_INT_0, HRESP_ERR_INT=HRESP_ERR_INT_0, STATFF_INT=STATFF_INT_0, DMA_TSF_DONE_FB1=DMA_TSF_DONE_FB1_0, DMA_TSF_DONE_SFF=DMA_TSF_DONE_SFF_0
CSI Status Register
| DRDY | RXFIFO Data Ready 0 (DRDY_0): No data (word) is ready 1 (DRDY_1): At least 1 datum (word) is ready in RXFIFO. |
| ECC_INT | CCIR Error Interrupt 0 (ECC_INT_0): No error detected 1 (ECC_INT_1): Error is detected in CCIR coding |
| HRESP_ERR_INT | Hresponse Error Interrupt Status 0 (HRESP_ERR_INT_0): No hresponse error. 1 (HRESP_ERR_INT_1): Hresponse error is detected. |
| COF_INT | Change Of Field Interrupt Status 0 (COF_INT_0): Video field has no change. 1 (COF_INT_1): Change of video field is detected. |
| F1_INT | CCIR Field 1 Interrupt Status 0 (F1_INT_0): Field 1 of video is not detected. 1 (F1_INT_1): Field 1 of video is about to start. |
| F2_INT | CCIR Field 2 Interrupt Status 0 (F2_INT_0): Field 2 of video is not detected 1 (F2_INT_1): Field 2 of video is about to start |
| SOF_INT | Start of Frame Interrupt Status. Indicates when SOF is detected. (Cleared by writing 1) 0 (SOF_INT_0): SOF is not detected. 1 (SOF_INT_1): SOF is detected. |
| EOF_INT | End of Frame (EOF) Interrupt Status. Indicates when EOF is detected. (Cleared by writing 1) 0 (EOF_INT_0): EOF is not detected. 1 (EOF_INT_1): EOF is detected. |
| RxFF_INT | RXFIFO Full Interrupt Status 0 (RxFF_INT_0): RxFIFO is not full. 1 (RxFF_INT_1): RxFIFO is full. |
| DMA_TSF_DONE_FB1 | DMA Transfer Done in Frame Buffer1 0 (DMA_TSF_DONE_FB1_0): DMA transfer is not completed. 1 (DMA_TSF_DONE_FB1_1): DMA transfer is completed. |
| DMA_TSF_DONE_FB2 | DMA Transfer Done in Frame Buffer2 0 (DMA_TSF_DONE_FB2_0): DMA transfer is not completed. 1 (DMA_TSF_DONE_FB2_1): DMA transfer is completed. |
| STATFF_INT | STATFIFO Full Interrupt Status 0 (STATFF_INT_0): STATFIFO is not full. 1 (STATFF_INT_1): STATFIFO is full. |
| DMA_TSF_DONE_SFF | DMA Transfer Done from StatFIFO 0 (DMA_TSF_DONE_SFF_0): DMA transfer is not completed. 1 (DMA_TSF_DONE_SFF_1): DMA transfer is completed. |
| RF_OR_INT | RxFIFO Overrun Interrupt Status 0 (RF_OR_INT_0): RXFIFO has not overflowed. 1 (RF_OR_INT_1): RXFIFO has overflowed. |
| SF_OR_INT | STATFIFO Overrun Interrupt Status 0 (SF_OR_INT_0): STATFIFO has not overflowed. 1 (SF_OR_INT_1): STATFIFO has overflowed. |
| DMA_FIELD1_DONE | When DMA field 0 is complete, this bit will be set to 1(clear by writing 1). |
| DMA_FIELD0_DONE | When DMA field 0 is complete, this bit will be set to 1(clear by writing 1). |
| BASEADDR_CHHANGE_ERROR | When using base address switching enable, this bit will be 1 when switching occur before DMA complete |